In the power layout of an integrated circuit, power grid connections and decoupling capacitors are implemented. Decoupling capacitance helps to prevent the integrated circuit from being affected by noise or voltage variations. In conventional methods, the power grid and decoupling capacitors are separately implemented. Because of the separate implementation, decoupling capacitors need extra time and efforts to be added to the power grid, and decoupling capacitance is not maximized in some cases.
Also, there can be wasted area with an irregular-shape layout (e.g., non-rectangular), especially when using multiple power domains, because the largest circuit block in the same power domain defines the boundary of a conventional power grid (e.g., rectangular).
Accordingly, new structures and methods for power layout are desired to improve on the above issues.